• <li id="00i08"><input id="00i08"></input></li>
  • <sup id="00i08"><tbody id="00i08"></tbody></sup>
    <abbr id="00i08"></abbr>
  • 新聞中心

    EEPW首頁 > 手機與無線通信 > 設計應用 > AD9547網絡時鐘與同步方案

    AD9547網絡時鐘與同步方案

    作者: 時間:2011-12-14 來源:網絡 收藏

    是雙路/四路輸入發生器/器,能為許多系統包括(SONET/SDH)提供.輸入基準頻率從1 kHz 到750 MHz,頻率監視1ppm,輸出頻率高達450MHz,主要應用在同步,OC-192的SONET/SDH,無線基站,控制器,有線基礎設備和數據通信. 本文介紹了主要特性, 功能方框圖,詳細方框圖, 輸出同步方框圖和評估板電路圖以及評估板材料清單.

    : Dual/Quad Input Network Clock Generator/Synchronizer

    The AD9547 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9547 generates an output clock that is synchronized to one of two differential or four single-ended external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The AD9547 continuously generates a clean (low jitter), valid output clock, even when all references fail, by means of digitally controlled loop and holdover circuitry. The AD9547 operates over an industrial temperature range of −40℃ to +85℃.

    AD9547主要特性:

    Supports Stratum 2 stability in holdover mode

    Supports reference switchover with phase build-out

    Supports hitless reference switchover

    Automatic/manual holdover and reference switchover

    2 pairs of reference input pins, with each pair configurable as a single differential input or as 2 independent single-ended inputs

    Input reference frequencies from 1 kHz to 750 MHz

    Reference validation and frequency monitoring (1 ppm)

    Programmable input reference switchover priority

    30-bit programmable input reference divider

    2 pairs of clock output pins, with each pair configurable as a single differential LVDS/LVPECL output or as 2 single-ended CMOS outputs

    Output frequencies up to 450 MHz

    20-bit integer and 10-bit fractional programmable feedback divider

    Programmable digital loop filter covering loop bandwidths from 0.001 Hz to 100 kHz

    Optional low noise LC-VCO system clock multiplier

    Optional crystal resonator for system clock input

    On-chip EEPROM to store multiple power-up profiles

    Software controlled power-down

    64-lead LFCSP package

    AD9547應用:

    Network synchronization

    Cleanup of reference clock jitter

    SONET/SDH clocks up to OC-192, including FEC

    Stratum 2 holdover, jitter cleanup, and phase transient control

    Stratum 3E and Stratum 3 reference clocks

    Wireless base stations, controllers

    Cable infrastructure

    Data communications

    圖1.AD9547功能方框圖

    本文引用地址:http://www.czjhyjcfj.com/article/155438.htm

    圖2.AD9547詳細方框圖


    上一頁 1 2 下一頁

    評論


    相關推薦

    技術專區

    關閉
    主站蜘蛛池模板: 大埔区| 北票市| 安陆市| 江门市| 郓城县| 唐海县| 修文县| 同仁县| 慈溪市| 肃南| 扎赉特旗| 山西省| 西乌| 保山市| 高州市| 额济纳旗| 凤凰县| 霍山县| 彰化市| 汤阴县| 东港市| 安陆市| 司法| 开化县| 大姚县| 小金县| 中宁县| 巴中市| 廉江市| 平遥县| 宣武区| 中牟县| 甘孜| 浏阳市| 桃园市| 武夷山市| 封丘县| 巴南区| 永川市| 西青区| 白水县|